Programmable gain amplifier with a large extent for the variation of gains

ABSTRACT

A programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of compensated metal oxide semiconductor or a bipolar junction transistor is disclosed. The structure of the programmable gain amplifier is divided into two stages, a first stage and a second stage. The first stage is formed by connecting a plurality of transistors in parallel, and the second stage is formed by a further plurality of transistors connected in parallel. The first stage and the second stage are connected in series. The current output end of transistors in the first stage each are connected to respective switches, respectively. Another, the current input end of transistors in the second stage each are connected to respective switches, respectively. Each of the switches is connected to a decoder. Therefore, through the control of the decoder, the on and off conditions of the switches can be determined so as to derive the required gain current.

1. FIELD OF THE INVENTION

The present invention relates to a programmable gain amplifier, and especially to a programmable gain amplifier with a large extent for the variation of gains, which is made by a manufacturing process of complementary metal oxide semiconductor (CMOS) or a bipolar junction transistor(BJT).

2. BACKGROUND OF THE INVENTION

Programmable gain amplifiers are very important in wireless communication system (such as GSM) requiring highly dynamic range. Therefore, a programmable gain amplifier with a larger gain controllable range and highly controllable linearity is beneficial to the whole effect of the system and complexity of the system. The gain control of a programmable gain amplifier can be achieved by changing the direct bias current (change gm of a transistor) and load resistance of an amplifier, wherein the maximum gain change is to control the bias current.

FIG. 1 shows a programmable gain amplifier with a varied gain range in the prior art design (U.S. Pat. No. 4,394,777), wherein the programmable gain amplifier includes a reference current generating circuit, a plurality of resistor elements, an auxiliary reference voltage generator, a plurality of switches which are connected to the resistor elements and a voltage to current converter. In the current gain control method, OP feedback circuit serves to control the depth of a MOS switch for adjusting the direct bias current of an amplifier or using fixed voltage to switch load resistor for change the value of current. While the abovesaid method has the following disadvantages: 1. The OP feedback circuit has a problem of stability. 2. It is difficult to control the depth of MOS switch. 3. The fixing voltage is used in the MOS manufacturing process, the variation of V_(T) causes that the performance of the circuit can not be controlled. 3. The layout of the resistors occupys a large area and the error in manufacturing process is large. 4. The structure of the circuit is complex. 5. Extra power consumption is required.

SUMMARY OF THE INVENTION

In order to increase the varied range of a gain and the precision of each gain level, and to be suitable for a low cost CMOS manufacturing process, the present invention discloses a new circuit structure for the current technology defect, and meanwhile, the difficult in design is reduced.

To achieve the aforesaid object, the present invention provides a programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of compensated metal oxide semiconductor or a bipolar junction transistor is disclosed. The structure is divided into two stages, a first stage and a second stage. The first stage is formed by connecting a plurality of transistors in parallel, and the second stage is formed by a further plurality of transistors in parallel. The first stage and the second stage are connected in series. The current output end of transistors in the first stage each are connected to respective switches, respectively. Another, the current input end of transistors in the second stage each are connected to respective switches, respectively. Each of the switches is connected to a decoder. Therefore, through the control of the decoder, the on and off conditions of the switches can be determined so as to derive the required bias current.

One of the programmable gain amplifier with a large extent for the variation of gains is made by a manufacturing process of compensated metal oxide semiconductor. The amount of current is determined wholly from the ratio of the transistor, therefore, the effect of error to the manufacturing process and the shift of temperature is very small. In a compensated metal oxide semiconductor, the gain in a amplifying stage is positively proportional to the transconduce (gm), while the value of gm is positively proportional to the square root value of the bias current (in bipolar, the gm is positively proportional to the bias current). Therefore, in the CMOS circuit, as the varied range of a programmable gain amplifier is enlarged, the varied range of the bias current in the gain stage is also very large, while the circuit structure of the present invention is suitable for this operation, otherwise, the advantages of this design core as following. The gates of CMOSs are not biased directly, therefore, the voltage change in the gate of the CMOS from errors will not effect the work of the circuit. The extra current consumed in the bias current can be avoided so as to achieve the object of power-saving. No resistance is used in the biasing and current control. Comparing with the way of controlling current by serially connecting resistors, the present invention uses smaller layout space and the effect of the error in the manufacturing process is reduced greatly. The required bias current is independently controlled by switches. For an amplifier necessary to precisely controlling the variation of gain, the difficult in design can be reduced.

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a programmable gain amplifier with a varied gain range in the prior art.

FIG. 2 is a circuit structure diagram of the a programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of complementary metal oxide semiconductor according to the present invention, wherein the circuit does not contain switches and decoder.

FIG. 3 is a circuit structure diagram of the a programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of complementary metal oxide semiconductor according to the present invention, wherein the circuit contains switches and decoder.

FIG. 4 is a circuit structure diagram of the a programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of bipolar junction transistor according to the present invention, wherein the circuit does not contain switches and decoder.

FIG. 5 is a circuit structure diagram of the a programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of bipolar junction transistor according to the present invention, wherein the circuit contains switches and decoder.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will be described in the following with the appended figures. Those skilled in the art should be understand that the following description is just as an example for causing those skilled in the art to full understand the present invention but not to used to confine the present invention.

In order to resolve the abovesaid prior art problem, the present invention discloses a novel design. FIGS. 2 and 3 show the first embodiment in the present invention, wherein a programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of compensated metal oxide semiconductor is illustrated. The structure is divided into two stages, a first stage and a second stage. The first stage is made by connecting PMOSs group, P₀ and P₁ to P_(N) in parallel, wherein P₁ to P_(N) are PMOS of different sizes. The second stage is installed by connecting NMOS N₀ and N₁ to N_(M) in parallel, wherein N₁ to N_(N) are NMOSs of different sizes. The width of CMOSs are W_(i) to W′i, respectively and the lengths are Li and L′, respectively, wherein i is equal to 0 to N. In the first stage, each transistor is biased by a bias current I_(bias) The I_(bais) is a stable current source. The mirror current I₁ to I_(N) is from the P₀ and P₁ to P_(N) for controlling the size. All these current flow to N₀, then by N₁. . . N_(M), mirror current I₁′ I_(M)′ are generated. The sum of I₁′˜I_(M)′ is I_(t), I_(t) is the bias current flowing through amplifier stage of the programmable gain amplifier, wherein I_(t) can be represented as: $\begin{matrix} {{It} = \quad {{Ibias} \times \left\lbrack {\frac{L_{0}}{W_{0}}\left( {\frac{W_{1}}{L_{1}} + \frac{W_{2}}{L_{2}} + \ldots + \frac{W_{N}}{L_{N}}} \right)} \right\rbrack \times}} \\ {\quad \left\lbrack {\frac{L_{0}^{\prime}}{W_{0}^{\prime}}\left( {\frac{W_{1}^{\prime}}{L_{1}^{\prime}} + \frac{W_{2}^{\prime}}{L_{2}^{\prime}} + \ldots + \frac{W_{M}^{\prime}}{L_{M}^{\prime}}} \right)} \right\rbrack} \end{matrix}$

where W_(i) and W′i are the width of CMOS, while Li and L′i are the length of the CMOS; and I_(bais) is the bias current source for voltage stability.

Referring to FIG. 3, in this embodiment, the drains of the transistor in the first stage is serially connected with switches, S₁˜SN_(N), and the source of the transistor in the second stage is serially connected to switches, S′₁˜S′_(M). The actions of P₁˜P_(N) is determined from the on-off conditions of the switches S₁˜S_(N). The action of N₁′˜N_(M)′ is controlled by the switches S₁′S_(M)′. These switches all are connected to a decoder. Therefore, the above equation can be represented as: $\begin{matrix} {{It} = \quad {{Ibias} \times \left\lbrack {A_{0}\quad \frac{L_{0}}{W_{0}}\left( {{A_{1}\quad \frac{W_{1}}{L_{1}}} + {A_{2}\quad \frac{W_{2}}{L_{2}}} + \ldots + {A_{N}\quad \frac{W_{N}}{L_{N}}}} \right)} \right\rbrack \times}} \\ {\quad \left\lbrack {A_{0}^{\prime}\quad \frac{L_{0}^{\prime}}{W_{0}^{\prime}}\left( {{A_{1}^{\prime}\quad \frac{W_{1}^{\prime}}{L_{1}^{\prime}}} + {A_{2}^{\prime}\quad \frac{W_{2}^{\prime}}{L_{2}^{\prime}}} + \ldots + {A_{N}^{\prime}\quad \frac{W_{N}^{\prime}}{L_{N}^{\prime}}}} \right)} \right\rbrack} \end{matrix}$

wherein the as the switch Si is conductive, Ai is 1, while as switch Si is not conductive, then Ai is 0. When the switch S′i is conductive, then A′i is 1, while as switch S′i is not conductive, then A′i is 0.

Therefore, through the control of the decoder D to determine which ones of the current I₁-I_(N) and I′₁-I′_(N) should be operated, the required gain current can be obtained. That is, as a required gain is obtained, the decoder will determine the conditions of all the switches according to above equation (i.e., to determine the required ratios of the (W/L)s).

FIGS. 4 and 5 show the first embodiment in the present invention, wherein a programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of bipolar junction transistor is illustrated. The structure is divided into two stages, a first stage and a second stage. The first stage is made by connecting bipolar junction transistor group, P″₀ and P″₁ to P″_(N) in parallel, wherein P″₁ to P∴_(N) are PNP bipolar junction transistor of different sizes. The second stage is installed by connecting bipolar junction transistor N″₀ and N″₁ to N″_(M) in parallel, wherein N″₁ to N″_(N) are NPN bipolar junction transistor of different sizes. The sizes of bipolar junction transistors are Bi to B′i, respectively, wherein i is equal to 0 to the larger one of N and M. In the first stage, the current in the gate of each transistor is provided by a bias current I_(bais). The I_(bias) is a stable current source. The mirror current I″₁ to I″_(N) is from the P″₀ and P″₁ to P″_(N) for controlling the size. All these current are flow to N″₀, then by N″₁ N″_(M), mirror current I′″₁′ I′″_(M)′ are generated. The sum of I′″₁′˜I′″_(M)′ is I′_(t), I′_(t) is the bias current flowing through the amplifier stage of the programmable gain amplifier, wherein I_(t) can be represented as: ${I^{\prime}t} = {{Ibias} \times \left\lbrack {\frac{1}{B_{0}}\quad \left( {B_{1} + B_{2} + \ldots + B_{N}} \right)} \right\rbrack \times \left\lbrack {\frac{1}{B_{0}}\quad \left( {B_{1} + B_{2} + \ldots + B_{M}} \right\rbrack} \right.}$

where Bi and B′i are sizes of bipolar junction transistor.

Referring to FIG. 5, in this embodiment, each the collector of the transistor in the first stage is serially connected with a switch, S₁˜S_(N), and the collector of the transistor in the second stage is serially connected to a switch, S′₁˜S′_(M). The actions of P₁˜P_(N) is determined from the on-off conditions of the switches S₁˜S_(N). The action of N₁′˜N_(M)′ is controlled by the switch S₁′˜S_(M)′. These switches all are connected to a decoder. Therefore, the above equation can be represented as: $\begin{matrix} {{I^{\prime}t} = \quad {{Ibias} \times \left\lbrack {A_{0}\quad \frac{1}{B_{0}}\quad \left( {{A_{1}B_{1}} + {A_{2}B_{2}} + \ldots + {A_{N}B_{N}}} \right)} \right\rbrack \times}} \\ {\quad \left\lbrack {A_{0}^{\prime}\quad \frac{1}{B_{0}}\quad \left( {{A_{1}^{\prime}B_{1}} + {A_{2}^{\prime}B_{2}} + \ldots + {A_{M}^{\prime}B_{M}}} \right\rbrack} \right.} \end{matrix}$

wherein the as the switch Si is conductive, Ai is 1, while as switch Si is not conductive, then Ai is 0. When the switch S′i is conductive, then A′i is 1, while as switch S′i is not conductive, then A′i is 0.

Therefore, through the control of the decoder D to determine which ones of the current I₁-I_(N) and I′₁-I′_(N) should be operated, the required gain current can be obtained. That is, as a required gain is obtained, the decoder will determine the conditions of all the switches according to above equation (i.e., to determine the required sizes of the bipolar junction transistor). By this way, the It can be controller in a range of 20 μ A to several mA and required current can be calculated precisely.

The advantages of this circuit structure are:

1. The amount of current is determined wholly from the ratio of the transistor, therefore, the effect of error to the manufacturing process and the shift of temperature is very small.

2. In a complementary metal oxide semiconductor, the gain in a amplifying stage is positively proportional to the transconduce (gm), while the size of gm is positively proportional to the square root value of the bias current (in bipolar, the gin is positively proportional to the bias current), therefore, in the CMOS circuit, as the varied range of a programmable gain amplifier is enlarged, the varied range of the bias current in the gain stage is also very large, while the circuit structure of the present invention is suitable for this operation.

3. The gates of CMOSs are not biased directly, therefore, the V_(T) change in the process of the CMOS from errors will not effect the work of the circuit.

4. The last bias current I_(t) is from the multiples of l_(bias), thus in a large current operation, the extra current consumed in the bias current can be avoided so as to achieve the object of power-saving.

5. No resistance is used in the biasing and current control. Comparing with the way of controlling current by serially connecting resistors, the present invention uses smaller layout space and the effect of the error in the manufacturing process is reduced greatly.

6. The required bias current is independently controlled by switch S₁˜S_(N) and S₁′˜S_(N)′. For an amplifier necessary to precisely controlling the variation of gain, the difficult in design can be reduced.

The present invention are thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the present invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims. 

What is claimed is:
 1. A programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of complementary metal oxide semiconductor (CMOS); wherein the structure is divided into two stages, a first stage and a second stage; the first stage is made by connecting PMOSs group, P₀ and P₁ to P_(N) in parallel, wherein P₁ to P_(N) are PMOS of different sizes; the second stage is installed by connecting NMOS N₀ and N₁ to N_(M) in parallel, wherein N₁ to N_(N) are NMOSs of different sizes; widths of CMOSs are Wi to W′i, respectively and the lengths are Li and L′, respectively, wherein i is equal to 0 to N, in the first stage, each transistor is biased by a bias current I_(bais).; then bias current I_(t) flowing through amplifier stage of the programmable gain amplifier is: $\begin{matrix} {{It} = \quad {{Ibias} \times \left\lbrack {\frac{L_{0}}{W_{0}}\left( {\frac{W_{1}}{L_{1}} + \frac{W_{2}}{L_{2}} + \ldots + \frac{W_{N}}{L_{N}}} \right)} \right\rbrack \times}} \\ {\quad \left\lbrack {\frac{L_{0}^{\prime}}{W_{0}^{\prime}}\left( {\frac{W_{1}^{\prime}}{L_{1}^{\prime}} + \frac{W_{2}^{\prime}}{L_{2}^{\prime}} + \ldots + \frac{W_{M}^{\prime}}{L_{M}^{\prime}}} \right)} \right\rbrack} \end{matrix}$

where Wi and W′i are the width of CMOS, while Li and L′i are the length of the CMOS; and I_(bias) is the bias current source for voltage stability.
 2. The programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of compensated metal oxide semiconductor as claimed in claim 1, wherein drains of transistors in the first stage are serially connected with switches, S₁˜S_(N), respectively, and sources of transistors in the second stage are serially connected to switches, S′₁˜S′_(M); actions of P₁˜P_(N) are determined from the on-off conditions of the switches S₁˜S_(N). and actions of N₁′˜N_(M)′ are controlled by the switch S₁′˜S_(M)′; therefore, the above equation is represented as: $\begin{matrix} {{It} = \quad {{Ibias} \times \left\lbrack {A_{0}\quad \frac{L_{0}}{W_{0}}\left( {{A_{1}\quad \frac{W_{1}}{L_{1}}} + {A_{2}\quad \frac{W_{2}}{L_{2}}} + \ldots + {A_{N}\quad \frac{W_{N}}{L_{N}}}} \right)} \right\rbrack \times}} \\ {\quad \left\lbrack {A_{0}^{\prime}\quad \frac{L_{0}^{\prime}}{W_{0}^{\prime}}\left( {{A_{1}^{\prime}\quad \frac{W_{1}^{\prime}}{L_{1}^{\prime}}} + {A_{2}^{\prime}\quad \frac{W_{2}^{\prime}}{L_{2}^{\prime}}} + \ldots + {A_{N}^{\prime}\quad \frac{W_{N}^{\prime}}{L_{N}^{\prime}}}} \right)} \right\rbrack} \end{matrix}$

where as the switch Si is conductive, Ai is 1, while as switch Si is not conductive, then Ai is 0; when the switch S′i is conductive, then A′i is 1, while as switch S′i is not conductive, then A′i is
 0. 3. The programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of complementary metal oxide semiconductor as claimed in claim 1, wherein all switches are connected to a decoder in parallel; through the control of the decoder D to determine which ones of the current I₁-I_(N) and I′₁-I′_(N) should be operated, a required gain current can be obtained; that is, as it wants to obtain a required gain, the decoder will determine the on and off conditions of all the switches according to above equation (i.e., to determine the required ratios of the (W/L)s).
 4. A programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of bipolar junction transistor, wherein the structure is divided into two stages, a first stage and a second stage, the first stage is made by a connecting bipolar junction transistor group, P″₀ and P″₁ to P″_(N) in parallel, wherein P″₁ to P″_(N) are PNP bipolar junction transistor of different sizes; the second stage is installed by connecting bipolar junction transistor N″₀ and N″₁ to N″_(M) in parallel, wherein N″₁ to N″_(N) are NPN bipolar junction transistor of different sizes; the sizes of bipolar junction transistors are Bi to B′i, respectively, wherein i is equal to 0 to the larger one of N and M; in the first stage, each transistor is biased by a bias current I_(bias); where I_(bias) is a stable bias current source for voltage stability; I′_(t) is the bias current flowing through the amplifier stage of the programmable gain amplifier, thus, I_(t) can be represented as: ${I^{\prime}t} = {{Ibias} \times \left\lbrack {\frac{1}{B_{0}}\quad \left( {B_{1} + B_{2} + \ldots + B_{N}} \right)} \right\rbrack \times \left\lbrack {\frac{1}{B_{0}}\quad \left( {B_{1} + B_{2} + \ldots + B_{M}} \right\rbrack} \right.}$

where Bi and B′i are sizes of bipolar junction transistor.
 5. The programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of bipolar junction transistor as claimed in claim 4, wherein each the collector of the transistor in the first stage is serially connected with switches, S₁˜S_(N), and the collectors of the transistors in the second stage are serially connected to switches, S′₁˜S′_(M), actions of P₁˜P_(N) are determined from the on-off conditions of the switches S₁˜S_(N), actions of N₁′˜N_(M)′ are controlled by the switches S₁′˜S_(M)′; therefore, the above equation can be represented as: $\begin{matrix} {{I^{\prime}t} = \quad {{Ibias} \times \left\lbrack {A_{0}\quad \frac{1}{B_{0}}\quad \left( {{A_{1}B_{1}} + {A_{2}B_{2}} + \ldots + {A_{N}B_{N}}} \right)} \right\rbrack \times}} \\ {\quad \left\lbrack {A_{0}^{\prime}\quad \frac{1}{B_{0}}\quad \left( {{A_{1}^{\prime}B_{1}} + {A_{2}^{\prime}B_{2}} + \ldots + {A_{M}^{\prime}B_{M}}} \right\rbrack} \right.} \end{matrix}$

wherein as the switch Si is conductive, Ai is 1, while as switch Si is not conductive, then Ai is
 0. When the switch S′i is conductive, then A′i is 1, while as switch S′i is not conductive, then A′i is
 0. 6. The programmable gain amplifier with a large extent for the variation of gains made by a manufacturing process of bipolar junction transistor as claimed in claim 4, wherein all switches are connected to a decoder in parallel; through the control of the decoder D to determine which ones of the current I₁-I_(N) and I′₁-I′_(N) should be operated, the required gain current can be obtained; that is, as it wants to acquire a required gain, the decoder will determine the conditions of all the switches according to above equation (i.e., to determine the required sizes of the bipolar junction transistor). 